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Microprocessor architecture: from simple pipelines to chip multiprocessors

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Abstract:
This book gives a comprehensive description of the architecture of microprocessors from simple in-order short pipeline designs to out-of order superscalars. It discusses topics such as:
• The policies and mechanisms needed for out-of order processing, such as register, renaming, reservation stations, and reorder buffers
• Optimizations for high performance, such as branch predictors, instruction scheduling, and load-store speculations
• Design choices and enhancements to tolerate latency in the cache hierarchy of single and multiple processors
• State-of-the art multithreading and multiprocessing, emphasizing single-chip implementations

TABLE OF CONTENT:
Introduction
A Quick View of Technological Advances
Performance Metrics
Performance Evaluation
Summary
Further Reading and Bibliographical Notes
The Basics
Pipelining
Caches
Virtual Memory and Paging
Summary
Further Reading and Bibliographical Notes
Superscalar Processors
From Scalar to Superscalar Processors
Overview of the Instruction Pipeline of the DEC Alpha 21164
Introducing Register Renaming, Reorder Buffer, and Reservation Stations
Overview of the Pentium P6 Microarchitecture
VLIW/EPIC Processors
Summary
Further Reading and Bibliographical Notes
Front-End: Branch Prediction, Instruction Fetching, and Register Renaming
Branch Prediction 130 Sidebar: The DEC Alpha 21264 Branch Predictor
Instruction Fetching
Decoding
Register Renaming (a Second Look)
Summary
Further Reading and Bibliographical Notes
Back-End: Instruction Scheduling, Memory Access Instructions, and Cluster
Instruction Issue and Scheduling (Wakeup and Select)
Memory-Accessing Instructions
Back-End Optimizations
Summary
Further Reading and Bibliographical Notes
The Cache Hierarchy
Improving Access to L1 Caches
Hiding Memory Latencies
Design Issues for Large Higher-Level Caches
Main Memory
Summary
Further Reading and Bibliographical Notes
Multiprocessors
Multiprocessor Organization
Cache Coherence
Synchronization
Relaxed Memory Models
Multimedia Instruction Set Extensions
Summary
Further Reading and Bibliographical Notes
Multithreading and (Chip) Multiprocessing
Single-Processor Multithreading
General-Purpose Multithreaded Chip Multiprocessors
Special-Purpose Multithreaded Chip Multiprocessors
Summary
Further Reading and Bibliographical Notes
Current Limitations and Future Challenges
Power and Thermal Management
Technological Limitations: Wire Delays and Pipeline Depths
Challenges for Chip Multiprocessors
Summary
Further Reading and Bibliographical Notes

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Availability

Detail Information

Series Title

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Call Number

004.22 BAE m

Publisher

New York : Cambridge University Press., 2010

Collation

xiv, 367 hlm.; ilus.; 26 cm.

Language

English

ISBN/ISSN

9780521769921

Classification

004.22

Content Type

-

Media Type

-

Carrier Type

-

Edition

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Subject(s)

Microprocessor
Mikroprosesor
COM (Computer Architecture)

Specific Detail Info

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Statement of Responsibility

Jean-Loup Baer

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