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Integrated circuit design

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Terdapat bibliografi dan indeks.

CONTENTS:
1. Welcome to VLSI
1.1 A Brief History
1.2 Preview
1.3 MOS Transistors
1.4 CMOS Logic
1.4.1 The Inverter
1.4.2 The NAND Gate
1.4.3 CMOS Logic Gates
1.4.4 The NOR Gate
1.4.5 Compound Gates
1.4.6 Pass Transistors and Transmission Gates
1.4.7 Tristates
1.4.8 Multiplexers
1.4.9 Sequential Circuits
1.5 CMOS Fabrication and Layout
1.5.1 Inverter Cross-Section
1.5.2 Fabrication Process
1.5.3 Layout Design Rules
1.5.4 Gate Layouts
1.5.5 Stick Diagrams
1.6 Design Partitioning
1.6.1 Design Abstractions
1.6.2 Structured Design
1.6.3 Behavioral, Structural, and Physical Domains
1.7 Example: A Simple MIPS Microprocessor
1.7.1 MIPS Architecture
1.7.2 Multicycle MIPS Microarchitectures
1.8 Logic Design
1.8.1 Top-Level Interfaces
1.8.2 Block Diagrams
1.8.3 Hierarchy
1.8.4 Hardware Description Languages
1.9 Circuit Design
1.10 Physical Design
1.10.1 Floorplanning
1.10.2 Standard Cells
1.10.3 Pitch Matching
1.10.4 Slice Plans
1.10.5 Arrays
1.10.6 Area Estimation
1.11 Design Verification
1.12 Fabrication, Packaging, and Testing

2. Devices
2.1 Introduction
2.2 Long-Channel I-V Characteristics
2.3 C-V Characteristics
2.4 Nonideal I-V Effects
2.5 DC Transfer Characteristics
2.6 Pitfalls and Fallacies

3. Speed
3.1 Introduction
3.2 Transiet Response
3.3 RC Delay Model
3.4 Linear Delay Model
3.5 Logical Effort of Paths
3.6 Timing analysis Delay Models
3.7 Pitfalls and Fallacies
3.8 Historical Perspective
4. Power
4.1 Introduction
4.2 Dynamic Power
4.3 Static Powerl
4.4 Energy-Delay Optimization
4.5 Low Power Architectures
4.7 Pitfalls and Fallacies
4.8 Historical Perspective

5. Wires
5.1 Introduction
5.2 Interconnect Modeling
5.3 Interconnect Impact
5.4 Interconnect Engineering
5.5 Logical Effort with Wires
5.6 Pitfalls and Fallacies

6. Scaling, Reliability and Variability
6.1 Introduction
6.2 Variability
6.3 Reliability
6.4 Scaling
6.5 Statistical Analysis of Variability
6.6 Variation-Tolerant Design

7. Chapter 7 SPICE
7.1 Introduction
7.2 A Spice Tutorial
7.3 Device Models
7.4 Device Characterization
7.5 Circuit Characterization
7.6 Interconnect Simulation
7.7 Pitfalls and Fallacies

8. 8. Gates
8.1 Introduction
8.2 Circuit Families
8.3 Circuit Pitfalls
8.4 Silicon-On-Insulator Circuit Design
8.5 Subthreshold Circuit Design
8.6 Pitfalls and Fallacies
8.7 Historical Perspective

9. Sequencing
9.1 Introduction
9.2 Sequencing Static Circuits
9.3 Circuit Design of Latches and Flip-Flops
9.4 Static Sequencing Element Methodology
9.5 Synchronizers
9.6 Wave Pipelining
9.7 Pitfalls and Fallacies

10. Datapaths
10.1 Introduction
10.2 Addition/Subtraction
10.3 One/Zero Detectors
10.4 Comparators
10.5 Counters
10.6 Boolean Logical Operations
10.7 Coding
10.8 Shifters
10.9 Multiplication
10.10 Parallel-Prefix Computations
10.11 Pitfalls and Fallacies

11. Memories
11.1 Introduction
11.2 SRAM
11.3 DRAM
11.4 Read-Only Memory
11.5 Serial Access Memories
11.6 Content-Addressable Memory
11.7 Programmable Logic Arrays
11.8 Robust Memory Design
11.9 Historical Perspective

12. Packaging, Power, Clock, I/O
12.1 Introduction
12.2 Packaging and Cooling
12.3 Power Distribution
12.4 Clocks
12.5 PLLs and DLLs
12.6 I/O
12.7 High-Speed Links
12.8 Random Circuits
12.9 Pitfalls and Fallacies

13. Methodology
13.1 Introduction
13.2 Structured Design Strategies
13.3 Design Methods
13.4 Design Flows
13.5 Design Economics
13.6 Data Sheets and Documentation
13.7 Pitfalls and Fallacies

14. Test
14.1 Introduction
14.2 Testers, Test Fixtures and Test Programs
14.3 Logic Verification Principles
14.4 Silicon Debug Principles
14.5 Manufacturing Test Principles
14.6 Design for Testability
14.7 Boundary Scan
14.8 Testing in a University Environment
14.9 Pitfalls and Fallacies

15. Fabrication
15.1 Introduction
15.2 CMOS Technologies
15.3 Layout Design Rules
15.4 CMOS Process Enhancements
15.5 Technology-Related CAD Issues
15.6 Manufacturing Issues
15.7 Pitfalls and Fallacies
15.8 Historical Perspective

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Availability

Detail Information

Series Title

null

Call Number

621.3815 WES i

Publisher

Boston : Pearson Education., 2011

Collation

xxiii, 751 hlm.; ilus.; 25 cm.

Language

English

ISBN/ISSN

9780321696946

Classification

621.3815

Content Type

-

Media Type

-

Carrier Type

-

Edition

fourth edition

Subject(s)

tenaga listrik, distribusi
Arus listrik
Listrik
Integrated Circuits-Design and Construction

Specific Detail Info

-

Statement of Responsibility

Neil H. E. Weste dan David Money Harris

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